1. Field of the Invention
The present invention relates to a fully differential amplifier, and more specifically to a fully differential amplifier so configured that an operating point potential of positive and negative output terminals of a differential amplifier having an active load is controlled by a common-mode feedback circuit.
2. Description of Related Art
A common-mode feedback circuit incorporated in a fully differential amplifier is ordinarily provided to set an operating potential of inverted and non-inverted output terminals of the fully differential amplifier. An example of the common-mode feedback circuit is described in Roubik Gregorian et al "ANALOG MOS INTEGRATED CIRCUITS FOR SIGNAL PROCESSING", Pages 254-256, A Wiley-Interscience Publication, 1986, the content of which is incorporated by reference in its entirety into this specification. However, this common-mode feedback circuit has only a narrow output operating range, because a number of transistors are series-connected between a positive voltage supply line and a negative voltage supply line. In addition, in order to freely set an output voltage, it is necessary to adjust the area of various circuit elements. In conclusion, this common-mode feedback circuit was very complicated in design.
In order to improve the above mentioned common-mode feedback circuit, it has been considered to detect a neutral point (common-mode output potential) between a positive output terminal and a negative output terminal of the fully differential amplifier, to compare the detected common-mode output potential with a reference potential, and to feed back the result of comparison to a control electrode of a transistor which constitutes an active load for the fully differential amplifier, for the purpose of equalizing the common-mode output potential with the reference potential. However, in a cascaded type of fully differential amplifier, if a resistor is directly connected to the output terminal so that a potential on the neutral point is detected by use of a resistor voltage division, a gain lowers, and therefore, an advantage of the cascaded type cannot be exerted.
Under this circumstance, it has been proposed to interpose a high impedance buffer and to detect the common-mode output potential from an output of the high impedance buffer by means of a voltage division resistor or a current addition. One typical example of this type fully differential amplifier will be described with reference to Japanese Patent Application Laid-open No. JP-A-01-126811, which discloses the differential amplifier applied with the current addition method, and the content of which is incorporated by reference in its entirety into this specification.
Referring to FIG. 1, there is shown a circuit diagram of the fully differential amplifier disclosed in the above identified Japanese patent application publication. In the shown fully differential amplifier, voltage controlled current circuits 100 and 200 are connected to output terminals 19 and 18 of a core amplifier 500, respectively, for the purpose of convening each output voltage into a current. The currents thus obtained am combined by a sum current transmission circuit 300 so as to generate a sum current, which is compared at a node A with a reference current generated in a reference current transmission circuit 400. The result of comparison is fed back so as to control a gate voltage of transistors Q.sub.27 and Q.sub.28, which constitute a portion of an active load of the fully differential amplifier. With this feedback operation, the common-mode output voltage becomes equal with the reference potential V.sub.REF.
However, paying attention to the core amplifier 500, a connection node between a drain of a transistor Q.sub.23 and a source of a transistor Q.sub.25 and a connection node between a drain of a transistor Q.sub.24 and a source of a transistor Q.sub.26 are put in a low impedance condition, since a gate of each of the transistors Q.sub.24 and Q.sub.26 are grounded. Accordingly, poles of higher powers caused by a parasitic capacitance are moved into a high frequency zone, and therefore, a sufficient phase margin can be obtained by a pole of a primary power formed by a low load capacitance C.sub.L. As a result, the core amplifier can have a high cutoff frequency f.sub.T suitable for a high speed operation.
However, examining the common-mode feedback circuit, poles of higher powers in the common-mode loop are moved into a low frequency zone, because of parasitic capacitances C.sub.1 and C.sub.2 occurring in parallel to resistors R.sub.1 and R.sub.2 connected to sources of transistors Q.sub.32 and Q.sub.33, and because of a gate capacitance C.sub.3 of gates of transistors Q.sub.27 and Q.sub.28 which are control electrodes for applying the feedback through the common-mode feedback circuit. As a result, although the core amplifier 500 has a sufficient phase margin, it is necessary to increase the load capacitance C.sub.L in order to cause the common-mode feedback circuit to have a phase margin.
This is also true in a common-mode output detection method. Namely, because of a voltage division resistor and a gate capacitance of a transistor receiving a voltage obtained by the voltage division resistor, poles of higher powers in the common-mode loop are moved into a low frequency zone, with the result that the toad capacitance C.sub.L must be increased for the purpose of causing the common-mode feedback circuit to have a phase margin.